High-Performance DA-Converters by Martin Clara

Author:Martin Clara
Language: eng
Format: epub
Publisher: Springer Berlin Heidelberg, Berlin, Heidelberg

4.2.8 Full-Clock Interleaved Current Cells

Time-interleaving of converters is extensively used in A/D-converters to maximize the sampling rate [134–137]. A number of identical A/D-converters can be operated in parallel and their output appropriately combined to yield a higher effective sampling rate. Also in the D/A direction the effective sampling rate can be increased by time-interleaving two or more converters [138, 139]. This not only relaxes the internal clock speed of the DAC-cores, but, more importantly for linearity, also extends their reset phase, provided that each converter performs a Return-to-Zero cycle in-between its active conversion phases. With two D/A-converter cores, the reset period is already extended to a full clock cycle.

As shown in Fig. 4.25, the overall D/A-converter then consists of two interleaved DAC-cores. Each DAC is alternately active for a full clock period during which it delivers the output current. In the following clock period the DAC-core that was active in the previous sampling period is reset, while the other DAC-core delivers the output current corresponding to the actual input data. Because the two DAC-cores process alternate data samples, a multiplexer is required from a conceptual viewpoint [133]. In a practical realization the multiplexing can be easily accomplished by triggering data latches at the input of the sub-DACs with opposite phases of a divided version of the sampling clock [140, 141].4 Naturally, this operation can also be distributed among the single DAC-cells [93]. Since current sources ideally do not influence each other when connected together at a sufficiently low-impedance summing node, an interleaved current-based D/A-converter can either be described as two (or more) identical sub-DACs or as a single DAC with as many interleaved individual current cells–both models are completely equivalent from a system perspective.

Fig. 4.25Full-clock interleaved DAC-cores

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